1. Field of the Invention
The invention relates to a method for fabricating CMOS transistors in semiconductor devices, and more particularly, to a method for fabricating the isolation regions for SOI (Silicon-On-Insulator) CMOS transistors.
2. Description of the Prior Art
In the present days, silicon-on-insulator (SOI) structures are recognized as an ideal configuration to fabricate CMOS transistors. The SOI technology offers many advantages, such as applying a simpler fabrication sequence and resultant cross-section compared to circuits fabricated on bulk silicon. In addition, the SOI scheme also provides reduced capacitive coupling between various circuit elements over the entire IC (integrated circuit) chip, and in CMOS circuit latchup is eliminated. SOI still reduces the size and/or increases packing density that will increase the circuit speed. Finally, a minimum device separation is determined only by the limitations of lithography.
Although, the SOI technology can significantly reduce process complexity and thus improve the operation speed (referring to the article disclosed by M. Alles et al. and titled "Thin film silicon on insulator: an enabling technology" in Semiconductor international p. 67, 1997), however, as with all technologies, SOI structure has its own disadvantages. For example, active regions in SOI technology are poorer in crystalline quality than their counterparts in bulk silicon. In addition, the presence of an isolating substrate, or insulating layer, may complicate or prevent the adoption of effective defect- and impurity-gettering processes.
Nevertheless, SOI's potential advantages are sufficiently attractive that development work in this area remains quite active. For instance, there are several methods to form thin film SOI structure, such as separation by implanted oxygen (SIMOX) and full isolation by porous oxidized silicon (FIPOS) processes. However, there are also potential disadvantages existed in SIMOX and FIPOS technologies. For the SIMOX structure, it is difficult to recover silicon defects induced by the high energy/dose oxygen implant (referring to the overview in the IEEE Circuit and Devices Magazine p. 3, 1987, disclosed by H. T. Weaver et al.). Also, for the FIPOS method, the high quality n-epitaxial layer must be grown on p+/p- substrate or n+/n- substrate (referring to the article disclosed by L. A. Nefit et al. titled "Advanced in oxidized porous silicon for SOI" in IDEM Tech. Dig. p. 800, 1984). Further process sequences are therefore needed to overcome the above-mentioned disadvantages, which will significantly upgrade cost budget. A requirement has been arisen to disclose a process to form CMOS transistors for future high speed and lower power application with less simpler fabricating sequence and less cost budget.